ROii 8-TC Stable
● Greedy SchedulerTX Margin (Inter-Packet Gap) for hardware-safe GCL scheduling — No Best-Effort — Per-Board GCL
3D Shuttle Network Topology
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⏱ Timing Budget — TX Margin
TX Margin is a minimum inter-packet gap enforced between consecutive transmissions on the same link. Without this gap, packets are placed back-to-back with zero spacing — theoretically optimal but impossible on real hardware.
The margin absorbs timing uncertainties: PTP clock synchronization error (±1µs typical), GCL gate transition jitter (~0.5µs), and store-and-forward processing variation. Recommended values: 1–3 µs for LAN9662 hardware.
PTP Sync Error
±1 µs
IEEE 1588 grandmaster tolerance
GCL Transition
~0.5 µs
Gate open/close switching time
Processing Jitter
±0.5 µs
Store-and-forward variation
Safety Margin
2 µs
Configured TX margin value
Schedule Parameters
µs
µs
µs
µs
PCP → TC Assignment (8-TC Dedicated)
| PCP | TC | Flow | Type | Payload | Period | Tx Time |
|---|---|---|---|---|---|---|
| 7 | TC7 | f_lidar_fc | LiDAR G32 | 1248 B | 167 µs | 10.288 µs |
| 6 | TC6 | f_lidar_r | LiDAR G32 | 1248 B | 167 µs | 10.288 µs |
| 5 | TC5 | f_lidar_fl | LiDAR P40P | 1262 B | 536 µs | 10.400 µs |
| 4 | TC4 | f_lidar_fr | LiDAR P40P | 1262 B | 536 µs | 10.400 µs |
| 3 | TC3 | f_radar_f | Radar MRR | 64 B | 5000 µs | 0.816 µs |
| 2 | TC2 | f_radar_flc | Radar MRR | 64 B | 5000 µs | 0.816 µs |
| 1 | TC1 | f_radar_frc | Radar MRR | 64 B | 5000 µs | 0.816 µs |
| 0 | TC0 | f_radar_rlc + f_radar_rrc | Radar MRR ×2 | 64 B ea | 5000 µs | 0.816 µs |
Network Topology — All 1 Gbps Links
TX Margin Statistics
Per-Switch GCL — Gate Control by Egress Port
Board Configuration (LAN9662 GCL)
Per-Link GCL Timeline (Gantt)
Packet E2E Delay
Link Utilization
Packet Schedule Table
| Packet | Flow | Route | Release | End | E2E | Deadline | Slack | Status |
|---|
▶ Raw GCL Output (JSON)
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